As integrated circuit technology advances, the demand for increased packing density, low power dissipation per square centimeter and compatibility between the various technologies increases. High packing density, usually obtained through device shrinkage, requires highly sophisticated processing techniques such as E-beam lithography, reactive ion etching, transient annealings, etc. Lower power dissipation is normally obtained utilizing CMOS structures, in which the pullup device of the CMOS pair may be replaced by a complimentary load device.
Increased packing density for VLSI applications is primarily achieved through scaling down device dimensions. One method for scaling down the dimensions is to "vertically" integrate the chip by stacking active layers on top of each other and building devices therein. These are commonly referred to as "stacked CMOS" devices wherein the p-channel transistor in a CMOS pair is stacked on top of the n-channel transistor. An overview of stacked CMOS devices can be found in J.-P. Colinge, "Laser-Recrystallized Silicon As A Device-Worthy Material For SOI And 3D Integrated Circuits", Universite Catholique De Louvain Faculte Des Sciences Appliquees, September 1984, pp. 47-65; and C. E. Chen, H. W. Lam, S. D. S. Malhi, R. F. Pinizzotto, IEEE Electron Dev. Lett. 4,272, (1983).
Stacked CMOS devices are normally fabricated by first patterning an n-channel region. A gate oxide is then formed on top of the n-channel region followed by a first polycrystalline silicon layer to form the first layer of n-channel devices and various interconnects. A second layer of polycrystalline material is then deposited thereon. The second poly layer is patterned to form the sources and drains of a second layer of p-channel transistors and also the p-channel region thereof over select ones of the first layer n-channel transistors with the gates of the n-channel transistors being common to the p-channel devices. The last processing steps involve patterning metal interconnects to interconnect the various stacked devices in a given circuit. The use of stacked CMOS reduces the number of interconnects and contact holes. However, additional processing steps are necessary for providing the metallization pattern. It is desirable to provide a processing method for reducing the number of steps necessary to form the interconnects in the stacked CMOS circuits. Stacked CMOS devices are generally described in U.S. Pat. No. 4,554,572 and U.S. patent application Ser. No. 656,055, both assigned to Texas Instruments Incorporated.